/* SPDX-License-Identifier: LGPL-2.1-only */
/*
 * Author: Weijie Gao <hackpascal@gmail.com>
 *
 * ONFI4.2 NAND parameter page definitions
 */
#pragma once

#ifndef _UFPROG_ONFI_PARAM_PAGE_H_
#define _UFPROG_ONFI_PARAM_PAGE_H_

#include <ufprog/nand-param-page.h>

#define ONFI_PARAM_PAGE_SIZE				256

/* PP_SIGNATURE */
#define ONFI_SIGNATURE					0x49464E4F

#define ONFI_REVISION_OFFS				4
#define ONFI_REVISION_LEN				2
#define ONFI_REVISION_4_2				BIT(11)
#define ONFI_REVISION_4_1				BIT(10)
#define ONFI_REVISION_4_0				BIT(9)
#define ONFI_REVISION_3_2				BIT(8)
#define ONFI_REVISION_3_1				BIT(7)
#define ONFI_REVISION_3_0				BIT(6)
#define ONFI_REVISION_2_3				BIT(5)
#define ONFI_REVISION_2_2				BIT(4)
#define ONFI_REVISION_2_1				BIT(3)
#define ONFI_REVISION_2_0				BIT(2)
#define ONFI_REVISION_1_0				BIT(1)

#define ONFI_FEATURES_OFFS				6
#define ONFI_FEATURES_LEN				2
#define ONFI_FEATURE_PES				BIT(15)
#define ONFI_FEATURE_ZQ_CALIBRATION			BIT(14)
#define ONFI_FEATURE_NV_DDR3				BIT(13)
#define ONFI_FEATURE_EXT_VPP				BIT(12)
#define ONFI_FEATURE_VOLUME_ADDRESSING			BIT(11)
#define ONFI_FEATURE_NV_DDR2				BIT(10)
#define ONFI_FEATURE_EZ_NAND				BIT(9)
#define ONFI_FEATURE_PP_REG_CLR_ENHANCE			BIT(8)
#define ONFI_FEATURE_EXT_PARAM_PAGE			BIT(7)
#define ONFI_FEATURE_MULTI_PLANE_READ			BIT(6)
#define ONFI_FEATURE_NV_DDR				BIT(5)
#define ONFI_FEATURE_ODD_TO_EVEN_COPYBACK		BIT(4)
#define ONFI_FEATURE_MULTI_PLANE_PP_ERASE		BIT(3)
#define ONFI_FEATURE_NON_SEQ_PAGE_PROG			BIT(2)
#define ONFI_FEATURE_MULTI_LUN_OPS			BIT(1)
#define ONFI_FEATURE_BW_16BIT				BIT(0)

#define ONFI_OPTIONAL_CMDS_OFFS				8
#define ONFI_OPTIONAL_CMDS_LEN				2
#define ONFI_OPTIONAL_CMD_ZQ_CAL			BIT(13)
#define ONFI_OPTIONAL_CMD_LUN_GET_SET			BIT(12)
#define ONFI_OPTIONAL_CMD_ODT_CFG			BIT(11)
#define ONFI_OPTIONAL_CMD_VOLUME_SEL			BIT(10)
#define ONFI_OPTIONAL_CMD_RESET_LUN			BIT(9)
#define ONFI_OPTIONAL_CMD_SMALL_DATA_MOVE		BIT(8)
#define ONFI_OPTIONAL_CMD_ROW_ADDR_CHG			BIT(7)
#define ONFI_OPTIONAL_CMD_READ_COL_CHG_ENHANCED		BIT(6)
#define ONFI_OPTIONAL_CMD_READ_UNIQUE_ID		BIT(5)
#define ONFI_OPTIONAL_CMD_COPY_BACK			BIT(4)
#define ONFI_OPTIONAL_CMD_READ_STATUS_ENHANCED		BIT(3)
#define ONFI_OPTIONAL_CMD_GET_SET_FEATURE		BIT(2)
#define ONFI_OPTIONAL_CMD_READ_CACHE			BIT(1)
#define ONFI_OPTIONAL_CMD_PAGE_CACHE_PROGRAM		BIT(0)

#define ONFI_JTG_PRIMARY_ADV_CMDS_OFFS			10
#define ONFI_JTG_PRIMARY_ADV_CMDS_LEN			1
#define ONFI_JTG_CMD_MULT_PLANE_BLOCK_ERASE		BIT(3)
#define ONFI_JTG_CMD_MULT_PLANE_COPYBACK_PROG		BIT(2)
#define ONFI_JTG_CMD_MULT_PLANE_PAGE_PROG		BIT(1)
#define ONFI_JTG_CMD_MULT_PLANE_RAND_DATA_OUT		BIT(0)

#define ONFI_TRAINING_CMDS_OFFS				11
#define ONFI_TRAINING_CMDS_LEN				1
#define ONFI_TRAINING_CMD_WRITE_RX_DQ			BIT(4)
#define ONFI_TRAINING_CMD_WRITE_TX_DQ			BIT(3)
#define ONFI_TRAINING_CMD_READ_DQ			BIT(2)
#define ONFI_TRAINING_CMD_IMPLICIT_DCC			BIT(1)
#define ONFI_TRAINING_CMD_EXPLICIT_DCC			BIT(0)

#define ONFI_EXT_PARAM_PAGE_LEN_OFFS			12
#define ONFI_EXT_PARAM_PAGE_LEN_LEN			2

#define ONFI_NUM_PARAM_PAGES_OFFS			14
#define ONFI_NUM_PARAM_PAGES_LEN			1

#define ONFI_MANUF_ID_OFFS				64
#define ONFI_MANUF_ID_LEN				1

#define ONFI_DATE_CODE_OFFS				65
#define ONFI_DATE_CODE_LEN				2

#define ONFI_BAD_BLOCKS_MAX_PER_LUN_OFFS		103
#define ONFI_BAD_BLOCKS_MAX_PER_LUN_LEN			2

#define ONFI_BLOCK_ENDURANCE_OFFS			105
#define ONFI_BLOCK_ENDURANCE_LEN			2

#define ONFI_GUARANTEED_VALID_BEGIN_BLOCKS_OFFS		107
#define ONFI_GUARANTEED_VALID_BEGIN_BLOCKS_LEN		1

#define ONFI_GUARANTEED_VALID_BLOCK_ENDUR_OFFS		108
#define ONFI_GUARANTEED_VALID_BLOCK_ENDUR_LEN		2

#define ONFI_NUM_PROGS_PER_PAGE_OFFS			110
#define ONFI_NUM_PROGS_PER_PAGE_LEN			1

#define ONFI_ECC_BITS_OFFS				112
#define ONFI_ECC_BITS_LEN				1

#define ONFI_PLANE_ADDRESS_BITS_OFFS			113
#define ONFI_PLANE_ADDRESS_BITS_LEN			1

#define ONFI_MULTI_PLANE_OP_ATTR_OFFS			114
#define ONFI_MULTI_PLANE_OP_ATTR_LEN			1
#define ONFI_MP_OP_LOWER_BIT_XNOR_BA_RESTRICTION	BIT(5)
#define ONFI_MP_OP_READ_CACHE_SUPPORTED			BIT(4)
#define ONFI_MP_OP_CACHE_ADDRESS_RESTRICTION		BIT(3)
#define ONFI_MP_OP_PROGRAM_CACGE_SUPPORTEDS		BIT(2)
#define ONFI_MP_OP_NO_BLOCK_ADDRESS_RESTRICTION		BIT(1)
#define ONFI_MP_OP_CONCURRENT_MP_SUPPORTED		BIT(0)

#define ONFI_EZ_NAND_SUPPORT_OFFS			115
#define ONFI_EZ_NAND_SUPPORT_LEN			1
#define ONFI_EZ_NAND_COPYBACK_ADJACENCY			BIT(2)
#define ONFI_EZ_NAND_COPYBACK_OTHER_PLANE_LUN		BIT(1)
#define ONFI_EZ_NAND_AUTO_RETRY_EN_DIS			BIT(0)

#define ONFI_IO_PIN_MAX_CAPACITANCE_OFFS		128
#define ONFI_IO_PIN_MAX_CAPACITANCE_LEN			1

#define ONFI_SDR_TIMING_MODE_SUPPORT_OFFS		129
#define ONFI_SDR_TIMING_MODE_SUPPORT_LEN		2
#define ONFI_SDR_TIMING_MODE_5				BIT(5)
#define ONFI_SDR_TIMING_MODE_4				BIT(4)
#define ONFI_SDR_TIMING_MODE_3				BIT(3)
#define ONFI_SDR_TIMING_MODE_2				BIT(2)
#define ONFI_SDR_TIMING_MODE_1				BIT(1)
#define ONFI_SDR_TIMING_MODE_0				BIT(0)

#define ONFI_T_PROG_MAX_OFFS				133
#define ONFI_T_PROG_MAX_LEN				2

#define ONFI_T_BERS_MAX_OFFS				135
#define ONFI_T_BERS_MAX_LEN				2

#define ONFI_T_R_MAX_OFFS				137
#define ONFI_T_R_MAX_BITS				138

#define ONFI_T_CCS_MIN_OFFS				139
#define ONFI_T_CCS_MIN_LEN				2

#define ONFI_NV_DDR_TIMING_MODE_SUPPORT_OFFS		141
#define ONFI_NV_DDR_TIMING_MODE_SUPPORT_LEN		1
#define ONFI_NV_DDR_TIMING_MODE_5			BIT(5)
#define ONFI_NV_DDR_TIMING_MODE_4			BIT(4)
#define ONFI_NV_DDR_TIMING_MODE_3			BIT(3)
#define ONFI_NV_DDR_TIMING_MODE_2			BIT(2)
#define ONFI_NV_DDR_TIMING_MODE_1			BIT(1)
#define ONFI_NV_DDR_TIMING_MODE_0			BIT(0)

#define ONFI_NV_DDR2_TIMING_MODE_SUPPORT_OFFS		142
#define ONFI_NV_DDR2_TIMING_MODE_SUPPORT_LEN		1
#define ONFI_NV_DDR2_TIMING_MODE_7			BIT(7)
#define ONFI_NV_DDR2_TIMING_MODE_6			BIT(6)
#define ONFI_NV_DDR2_TIMING_MODE_5			BIT(5)
#define ONFI_NV_DDR2_TIMING_MODE_4			BIT(4)
#define ONFI_NV_DDR2_TIMING_MODE_3			BIT(3)
#define ONFI_NV_DDR2_TIMING_MODE_2			BIT(2)
#define ONFI_NV_DDR2_TIMING_MODE_1			BIT(1)
#define ONFI_NV_DDR2_TIMING_MODE_0			BIT(0)

#define ONFI_NV_DDR1_2_FEATURES_OFFS			143
#define ONFI_NV_DDR1_2_FEATURES_LEN			1
#define ONFI_NV_DDR1_2_FEATURE_REQ_VPP_EN_SEQ		BIT(3)
#define ONFI_NV_DDR1_2_FEATURE_SUPPORT_CLK_STOP		BIT(2)
#define ONFI_NV_DDR1_2_FEATURE_TYP_CAP_VALUES		BIT(1)
#define ONFI_NV_DDR1_2_FEATURE_T_CAD_VALUE		BIT(0)

#define ONFI_CLK_INPUT_TYP_CAPACITANCE_OFFS		144
#define ONFI_CLK_INPUT_TYP_CAPACITANCE_LEN		2

#define ONFI_IO_INPUT_TYP_CAPACITANCE_OFFS		146
#define ONFI_IO_INPUT_TYP_CAPACITANCE_LEN		2

#define ONFI_INPUT_TYP_CAPACITANCE_OFFS			148
#define ONFI_INPUT_TYP_CAPACITANCE_LEN			2

#define ONFI_INPUT_MAX_CAPACITANCE_OFFS			150
#define ONFI_INPUT_MAX_CAPACITANCE_LEN			1

#define ONFI_DRIVER_STRENGTH_SUPPORT_OFFS		151
#define ONFI_DRIVER_STRENGTH_SUPPORT_LEN		1
#define ONFI_DRIVER_STRENGTH_35_37P5_50_OHM		BIT(4)
#define ONFI_DRIVER_STRENGTH_37P5_50_OHM		BIT(3)
#define ONFI_DRIVER_STRENGTH_18OHM			BIT(2)
#define ONFI_DRIVER_STRENGTH_25OHM			BIT(1)
#define ONFI_DRIVER_STRENGTH_35_50_OHM			BIT(0)

#define ONFI_T_R_MAX_MULTI_PLANE_READ_US_OFFS		152
#define ONFI_T_R_MAX_MULTI_PLANE_READ_US_LEN		2

#define ONFI_T_ADL_PP_REG_CLEAR_ENHANCE_NS_OFFS		154
#define ONFI_T_ADL_PP_REG_CLEAR_ENHANCE_NS_LEN		2

#define ONFI_T_R_PAGE_READ_EZ_NAND_TYP_US_OFFS		156
#define ONFI_T_R_PAGE_READ_EZ_NAND_TYP_US_LEN		2

#define ONFI_NV_DDR2_3_FEATURES_OFFS			158
#define ONFI_NV_DDR2_3_FEATURES_LEN			1
#define ONFI_NV_DDR2_3_FEATURE_EXT_VREFQ_REQ		BIT(5)
#define ONFI_NV_DDR2_3_FEATURE_DQS_DIFF_SIGNAL		BIT(4)
#define ONFI_NV_DDR2_3_FEATURE_RE_N_DIFF_SIGNAL		BIT(3)
#define ONFI_NV_DDR2_3_FEATURE_ODT_30OHM		BIT(2)
#define ONFI_NV_DDR2_3_FEATURE_MATRIX_TERM_ODT		BIT(1)
#define ONFI_NV_DDR2_3_FEATURE_SELF_TERM_ODT		BIT(0)

#define ONFI_NV_DDR2_3_WARM_UP_CYCLES_OFFS		159
#define ONFI_NV_DDR2_3_WARM_UP_CYCLES_LEN		1
#define ONFI_NV_DDR2_3_WARM_UP_CYCLES_MASK		0xf
#define ONFI_NV_DDR2_3_WARM_UP_CYCLES_IN_SHIFT		4
#define ONFI_NV_DDR2_3_WARM_UP_CYCLES_OUT_SHIFT		0

#define ONFI_NV_DDR3_TIMING_MODE_SUPPORT_OFFS		160
#define ONFI_NV_DDR3_TIMING_MODE_SUPPORT_LEN		2
#define ONFI_NV_DDR3_TIMING_MODE_15			BIT(12)
#define ONFI_NV_DDR3_TIMING_MODE_14			BIT(11)
#define ONFI_NV_DDR3_TIMING_MODE_13			BIT(10)
#define ONFI_NV_DDR3_TIMING_MODE_12			BIT(9)
#define ONFI_NV_DDR3_TIMING_MODE_11			BIT(8)
#define ONFI_NV_DDR3_TIMING_MODE_10			BIT(7)
#define ONFI_NV_DDR3_TIMING_MODE_9			BIT(6)
#define ONFI_NV_DDR3_TIMING_MODE_8			BIT(5)
#define ONFI_NV_DDR3_TIMING_MODE_7			BIT(4)
#define ONFI_NV_DDR3_TIMING_MODE_6			BIT(3)
#define ONFI_NV_DDR3_TIMING_MODE_5			BIT(2)
#define ONFI_NV_DDR3_TIMING_MODE_4			BIT(1)
#define ONFI_NV_DDR3_TIMING_MODE_0_3			BIT(0)

#define ONFI_NV_DDR2_TIMING_MODE_SUPPORT2_OFFS		162
#define ONFI_NV_DDR2_TIMING_MODE_SUPPORT2_LEN		1
#define ONFI_NV_DDR2_TIMING_MODE_10			BIT(2)
#define ONFI_NV_DDR2_TIMING_MODE_9			BIT(1)
#define ONFI_NV_DDR2_TIMING_MODE_8			BIT(0)

#define ONFI_VENDOR_SPECIFIC_REV_NUM_OFFS		164
#define ONFI_VENDOR_SPECIFIC_REV_NUM_LEN		2

#define ONFI_VENDOR_BLOCK_OFFS				166

#define ONFI_CRC_OFFS					(ONFI_PARAM_PAGE_SIZE - PP_CRC_VAL_LEN)

/* Extended Parameter Page */

#define ONFI_EXT_SECT_NONE				0
#define ONFI_EXT_SECT_TYPE_LEN				1
#define ONFI_EXT_SECT_ECC_INFO				2

#define ONFI_EXT_CRC_OFFS				0
#define ONFI_EXT_CRC_LEN				2

#define ONFI_EXT_SIGNATURE_OFFS				2
#define ONFI_EXT_SIGNATURE_LEN				4
#define ONFI_EXT_SIGNATURE				0x53505045

#define ONFI_EXT_SECT_TYPE_OFFS				16
#define ONFI_EXT_SECT_TYPE_LEN				1

#define ONFI_EXT_SECT_LEN_OFFS				17
#define ONFI_EXT_SECT_LEN_LEN				1

#define ONFI_EXT_SECT_DATA_OFFS				32

static inline uint8_t onfi_read_mfr_id(const void *pp)
{
	return ufprog_pp_read_u8(pp, ONFI_MANUF_ID_OFFS);
}

const char *UFPROG_API ufprog_onfi_revision(const void *pp);

#endif /* _UFPROG_ONFI_PARAM_PAGE_H_ */
